F81867 Datasheet, PDF (254/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
FAN2 SEGMENT 3 SPEED COUNT Register – Offset BCh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN2_MODE(CR96)
7-0
SEC3SPEED2
R/W 5VSB ^{B2h 2’b00: The value that set in this byte is the relative expect fan}
(70%) _{speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 SEGMENT 4 SPEED COUNT Register – Offset BDh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN2_MODE(CR96)
99h ^{2’b00: The value that set in this byte is the relative expect fan}
7-0
SEC4SPEED2
R/W 5VSB _{(60%) speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 SEGMENT 5 SPEED COUNT Register – Offset BEh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN2_MODE(CR96)
80h _{2’b00: The value that set in this byte is the relative expect fan}
7-0
SEC5PEED2
R/W 5VSB (50%)
speed % of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 Temperature Mapping Select – Offset BFh
Bit
Name
R/W Reset Default
Description
FAN2_TEMP_
This bit companies with FAN2_TEMP_SEL to select the
7
R/W 5VSB 0
SEL_DIG
temperature source for controlling FAN2.
This bit and FREQ_SEL_ADD2 are used to select FAN2 PWM
frequency. NEW_FREQ_SEL2 = { FREQ_SEL_ADD2,
FAN2_PWM_FREQ_SEL}
FAN2_PWM_
6
R/W 5VSB 0 00: 23.5 KHz
FREQ_SEL
01: 11.75 KHz
10: 5.875 KHz
11: 220 Hz
Set 1 to force FAN2 to full speed if any temperature over its high
5 FAN2_UP_T_EN R/W 5VSB 0
limit.
254
Dec, 2011
V0.12P