F81867 Datasheet, PDF (205/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
R/W LRESET# 0 _{1: the SM2 bit will be cleared by hardware according to the sent address and}
the given address (or broadcast address derived by SADDR and SADEN)
5
RS485_INV
R/W LRESET# 0 Invert RTS# if RS485_EN is set.
0: RS232 driver.
4
RS485_EN
R/W LRESET# 0 1: RS485 driver. RTS# is driven high automatically when transmitting
data, otherwise is kept low.
0 : No reception delay when SIR is changed from TX to RX.
3
RXW4C_IR
R/W LRESET# 0 _{1 : Reception delay 4 character-time when SIR is changed from TX to RX.}
0 : No transmission delay when SIR is changed from RX to TX.
2
TXW4C_IR
R/W LRESET# 0 _{1 : Transmission delay 4 character-time when SIR is changed from RX to TX.}
IRQ_MODE1 and IRQ_MODE0 will select the UART5 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
1
IRQ_MODE0
R/W LRESET# 0 ^{01 : Sharing IRQ active high edge mode.}
10 : Sharing IRQ active high Level mode.
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0
IRQ_SHARE
R/W LRESET#
0
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
IR Mode Select Register ⎯ Index F1h
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
- Reserved. Return 010b when read.
0X: Disable IR1 function.
4-3
IRMODE1
R/W LRESET# 00b ^{10 : Enable IR1 function, active pulse is 1.6uS.}
IRMODE0
11 : Enable IR1 function, active pulse is 3/16 bit time.
0 : Full Duplex function for IR self test.
2
HDUPLX
R/W LRESET# 1 ^{1 : Half Duplex function.}
Return 1 when read.
0 : IRTX is not inversed.
1
TXINV_IR
R/W LRESET#
0 _{1 : Inverse the IRTX.}
0
RXINV_IR
R/W LRESET#
0 ^{0 : IRRX is not inversed.}
1 : Inverse the IRRX.
Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
Select the clock source for UART6.
00: 1.8432MHz.
1-0 UART6_CLK_SEL R/W LRESET# 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
205
Dec, 2011
V0.12P