F81867 Datasheet, PDF (262/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

GPIO0 Mode Register ⎯ offset F5h
Bit
Name
R/W Reset Default
Description
7-6 GPIO07_MODE R/W 5VSB
The output mode of GPIO07.
00: Level mode.
0 01: Inverted level mode.
10: High pulse mode.
11: Low pulse mode.
5-4 GPIO06_MODE R/W 5VSB
The output mode of GPIO06.
00: Level mode.
0 01: Inverted level mode.
10: High pulse mode.
11: Low pulse mode.
3-2 GPIO05_MODE R/W 5VSB
The output mode of GPIO05.
00: Level mode.
0 01: Inverted level mode.
10: High pulse mode.
11: Low pulse mode.
1-0 GPIO04_MODE R/W 5VSB
The output mode of GPIO04.
00: Level mode.
0 01: Inverted level mode.
10: High pulse mode.
11: Low pulse mode.
GPIO0 Pulse Select Register ⎯ offset F7h
Bit
Name
R/W Reset Default
Description
7-6 GPIO07_PW_SEL R/W 5VSB
The pulse width of GPIO07 in pulse output mode.
00: 500us.
0 01: 1ms.
10: 20ms.
11: 100ms.
5-4 GPIO06_PW_SEL R/W 5VSB
The pulse width of GPIO06 in pulse output mode.
00: 500us.
0 01: 1ms.
10: 20ms.
11: 100ms.
3-2 GPIO05_PW_SEL R/W 5VSB
The pulse width of GPIO05 in pulse output mode.
00: 500us.
0 01: 1ms.
10: 20ms.
11: 100ms.
1-0 GPIO04_PW_SEL R/W 5VSB
The pulse width of GPIO04 in pulse output mode.
00: 500us.
0 01: 1ms.
10: 20ms.
11: 100ms.
F81867
262
Dec, 2011
V0.12P