F81867 Datasheet, PDF (284/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

3 HOST_DIS_MO_CLK R
2 HOST_DIS_KB_CLK R
5VSB
5VSB
1 μC_DIS_MO_CLK R/W 5VSB
0 μC_DIS_KB_CLK R/W 5VSB
F81867
0 This bit represents the status of host disable mouse clock signal.
0 This bit represents the status of host disable keyboard clock signal.
0
Set “1” to disable PS/2 mouse interface. PS2_CTRL_EN switch the disable
signal between HOST_DIS_MO_CLK and μC_DIS_MO_CLK.
Set “1” to disable PS/2 keyboard interface. PS2_CTRL_EN switch the
0 _{disable signal between HOST_DIS_KB_CLK and μC_DIS_KB_CLK.}
KBC Status Register ⎯ Offset 02h
Bit
Name
R/W Reset Default
Description
7-0
KBC_STS
R 5VSB - The status of KBC. Same as 0x64 port of host side.
PS/2 Interrupt Enable Register ⎯ Offset 03h
Bit
Name
R/W Reset Default
Description
7 KBC_ST_INT_EN R/W 5VSB
0: Disable KBC status interrupt.
0
1: Enable KBC status interrupt. KBC_STS change will assert interrupt to μC.
6
Reserved
-
-
- Reserved.
0: Disable read mouse data interrupt.
5
MO_RD_IN_EN R/W 5VSB 0 1: Enable read mouse data interrupt. Host read mouse data will assert
interrupt to μC.
0: Disable read keyboard data interrupt.
4
KB_RD_IN_EN R/W 5VSB 0 1: Enable read keyboard data interrupt. Host read mouse data will assert
interrupt to μC.
3 MO_WR_INT_EN R/W 5VSB
0: Disable PS/2 mouse write command interrupt.
0 ^{1: Enable PS/2 mouse interface interrupt. An interrupt will be asserted to μC}
when the host write command to PS/2 mouse which will set
MO_WR_BYTE_ST.
0: Disable PS/2 keyboard write command interrupt.
2
KB_WR_INT_EN R/W 5VSB
0 ^{1: Enable PS/2 keyboard interface interrupt. An interrupt will be asserted to}
μC when host write command to PS/2 keyboard which will set
KB_WR_BYTE_ST.
1 MO_RCV_INT_EN R/W 5VSB
0: Disable PS/2 mouse interface receiving interrupt.
0 1: Enable PS/2 mouse interface receiving interrupt. An interrupt will be
asserted to μC when a byte is received which will set MO_RCV_BYTE_ST.
0 KB_RCV_INT_EN R/W 5VSB
0: Disable PS/2 keyboard interface receiving interrupt.
0 1: Enable PS/2 keyboard interface receiving interrupt. An interrupt will be
asserted to μC when a byte is received which will set KB_RCV_BYTE_ST.
PS/2 Receiving Status Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
Description
7 KBC_ST_CHG_ST R/WC 5VSB 0 This bit will be set when KBC_STS changes.
6
Reserved
-
-
- Reserved.
5
MO_RD_ST R/WC 5VSB 0 This bit will be set when host read mouse data.
4
KB_RD_ST
R/WC 5VSB
0 This bit will be set when host read keyboard data.
3 MO_WR_BYTE_ST R/WC 5VSB 0 This bit will be set when host write data to mouse. Write “1” to clear.
2 KB_WR_BYTE_ST R/WC 5VSB 0 This bit will be set when host write data to keyboard. Write “1” to clear.
284
Dec, 2011
V0.12P