82434LX Datasheet, PDF (98/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
5 1 5 FLUSH FLUSH ACKNOWLEDGE AND
WRITE-BACK SPECIAL CYCLES
There are three special cycles that affect the second
level cache flush flush acknowledge and write-
back If the processor executes an INVD instruction
it will invalidate all unmodified first level cache lines
and issue a flush special cycle If the processor exe-
cutes a WBINVD instruction it will write back all
modified first level cache lines invalidate the first
level cache and issue a write-back special cycle fol-
lowed by a flush special cycle If the Pentium proc-
essor FLUSH pin is asserted the CPU will write-
back all modified first level cache lines invalidate
the first level cache and issue a flush acknowledge
special cycle
The second level cache behaves the same way in
response to the flush special cycle and flush ac-
knowledge special cycle Each tag is read and the
valid and modified bits are examined If the line is
both valid and modified it is written back to main
memory and the valid bit for that line is reset All
valid and unmodified lines are simply marked invalid
The PCMC advances to the next tag when all lines
within the current sector have been examined
BRDY is returned to the Pentium processor after
all modified lines in the second level cache have
been written back to main memory and all of the
valid bits for the second level cache are reset The
sequence of write-back cycles will only be interrupt-
ed to service a PCI master cycle
The write-back special cycle is ignored by the PCMC
because all modified lines will be written back to
main memory by the following flush special cycle
Upon decoding a write-back special cycle the
PCMC simply returns BRDY to the Pentium proc-
essor
5 2 82434NX Cache
The 82434NX PCMC integrates a high performance
write-back second level cache controller tag RAM
and a full first and second level cache coherency
mechanism The cache is either 256 KBytes or
512 KBytes using either synchronous burst SRAMs
or standard asynchronous SRAMs Parity on the
data SRAMs is optional The cache uses a write-
back write policy Write-through mode is not support-
ed
The 82434NX PCMC supports a direct mapped sec-
ondary cache The PCMC contains 4096 tags Each
tag represents a sector in the cache If the cache is
512 KB each sector contains four cache lines If the
cache is 256 KB each sector contains two cache
lines Valid and Modified bits are kept on a per line
basis The 82434NX Tag RAM is 1 bit wider than the
82434LX Tag RAM
The PCMC can be configured to cache main memo-
ry on read cycles even when CACHE is not assert-
ed When bit 4 in the Secondary Cache Control Reg-
ister (offset 52h) is set to 1 all accesses to main
memory except those to SMM memory or any range
marked non-cacheable via the PAM registers are
cached in the secondary cache Accesses with
CACHE asserted result in a line fill in both the first
and second level cache while accesses with
CACHE negated result in a line fill only in the sec-
ond level cache When bit 4 in the SCC Register is
set to 0 only access with CACHE asserted can
generate a first and second level cache line fill
When a Halt or Stop Grant Special Cycle is detected
from the CPU the 82434NX PCMC places the sec-
ond level cache into the low power stand-by mode
by deselecting the SRAMs and then generates the
corresponding special cycle on PCI (i e if the CPU
cycle was a halt special cycle then the PCMC gener-
ates a halt special cycle on PCI and if the CPU cycle
is a stop grant special cycle the PCMC generates a
stop grant special cycle on PCI)
When a burst SRAM secondary cache is implement-
ed bit 2 of the Secondary Cache Control Register
(offset 52h) is used to select between 82434LX
SRAM connectivity and the new 82434NX SRAM
connectivity When set to 0 the secondary cache
interface is in 82430-compatible mode (i e the four
low order address lines on the SRAMs are connect-
ed to CAA B 6 3 on the PCMC When set to 1 sec-
ond level cache stand-by is enabled and no latch is
used between the host CPU address lines and the
SRAM address lines All of the SRAM address lines
are then connected directly to the CPU address
lines Write-back addresses are driven by the PCMC
over the host address lines When a standard SRAM
secondary cache is implemented bit 2 of the Sec-
ondary Cache Control Register (offset 52h) is used
to enable second level cache stand-by The default
value of this bit is 0
Figure 38 and Figure 41 show the connections be-
tween the PCMC and the external cache data
SRAMs and latch for the case of an asynchronous
SRAM cache
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