82434LX Datasheet, PDF (129/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 4 REFRESH
The refresh of the DRAM array can be performed by
either using RAS -only or CAS -before-RAS
refresh cycles When programmed for CAS -
before-RAS refresh hidden refresh cycles are
initiated when possible The timing of internally gen-
erated refresh cycles is derived from HCLK and is
independent of any expansion bus refresh cycles
The DRAM controller contains an internal refresh
timer which periodically requests the refresh control
logic to perform either a single refresh or a burst of
four refreshes The single refresh interval is 15 6 ms
The interval for burst of four refreshes is four times
the single refresh interval or 62 4 ms The PCMC is
configured for either single or burst of four refresh
and either RAS -only or CAS -before RAS re-
fresh via the DRAM Control Register (offset 57h)
To minimize performance impact refresh cycles are
partially deferred until the DRAM interface is idle
Refresh cycles are initiated such that the RAS
maximum active time is never violated
Hidden refresh cycles are run whenever all eight
CAS lines are active at the end of a read transac-
tion when the refresh cycle is internally requested
Normal CAS -before-RAS refresh cycles are run
whenever the DRAM interface is idle when the re-
fresh is requested or when any subset of the CAS
lines is inactive as the refresh is internally requested
To minimize the power surge for refreshing a large
DRAM array the DRAM interface staggers the as-
sertion and negation of the RAS signals during
both CAS -before-RAS and RAS -only refresh
cycles The order of RAS edges is dependent on
which RAS was most recently asserted prior to the
refresh sequence The RAS that was active will be
the last to be activated during the refresh sequence
All RAS 7 0 lines are negated at the end of re-
fresh cycles making the first DRAM cycle after a
refresh sequence a row miss
6 2 4 1 RAS -Only Refresh Single
Figure 61 depicts a RAS -only refresh cycle when
the 82434NX is programmed for single refresh cy-
cles The diagram shows a cycle completing as the
refresh timer inside the PCMC generates a refresh
request The refresh address is driven on the
MA 11 0 lines Since the cycle was to row 0
RAS0 is negated RAS1 is the first to be assert-
ed RAS2 through RAS7 are then asserted se-
quentially while RAS0 is driven high precharging
the DRAMs in row 0 RAS0 is then asserted after
RAS7 Each RAS line is asserted for eight host
clocks
Figure 61 RAS -Only Refresh Single
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