82434LX Datasheet, PDF (54/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
System BIOS Area (F0000h-FFFFFh)
This area is a single 64-KByte segment This segment can be assigned cacheability read and write attributes
When disabled this segment is not remapped
Extended Memory Area (100000h-FFFFFFFFh)
The extended memory area can be split into several parts
 Flash BIOS area from 4 GByte to 4 GByte–512-KByte (aliased on ISA at 16 MBytes–15 5 MBytes)
 DRAM Memory from 1 MByte to a maximum of 192 MBytes
 PCI Memory space from the top of DRAM to 4 GByte – 512-KByte
 Memory Space Gap between the range of 1 MByte up to 15 5 MBytes
 Frame Buffer Range mapped into PCI Memory Space or the Memory Space Gap
On power-up or reset the CPU vectors to the Flash BIOS area mapped in the range of 4 GByte to 4 GByte –
512-KByte This area is physically mapped on the expansion bus Since these addresses are in the upper
4 GByte range the request is directed to PCI
The DRAM memory space can occupy extended memory from a minimum of 2 MBytes up to 192 MBytes This
memory is cacheable
The address space on PCI between the Flash BIOS (4 GByte to 4 GByte – 512 KByte) and the top of DRAM
(including any remapped memory) may be occupied by PCI memory This memory space is not cacheable
3 2 20 DRB DRAM ROW BOUNDARY REGISTERS
Address Offset
Default Value
Attribute
Size
60–65h (82434LX)
60–67h (82434NX)
02h
Read Write
8 bits
Note the address offset for each DRB Register is DRB0^e60h DRB1^e61h DRB2^e62h DRB3^e63h
DRB4^e64h DRB5^e65h DRB6^e66h and DRB7^e67h
3 2 20 1 82434LX Description
The PCMC supports 6 rows of DRAM Each row is 64 bits wide The DRAM Row Boundary Registers define
upper and lower addresses for each DRAM row Contents of these 8-bit registers represent the boundary
addresses in MBytes
DRB0 ^e Total amount of memory in row 0 (in MBytes)
DRB1 ^e Total amount of memory in row 0 ^a row 1 (in MBytes)
DRB2 ^e Total amount of memory in row 0 ^a row 1 ^a row 2 (in MBytes)
DRB3 ^e Total amount of memory in row 0 ^a row 1 ^a row 2 ^a row 3 (in MBytes)
DRB4 ^e Total amount of memory in row 0 ^a row 1 ^a row 2 ^a row 3 ^a row 4 (in MBytes)
DRB5 ^e Total amount of memory in row 0 ^a row 1 ^a row 2 ^a row 3 ^a row 4 ^a row 5 (in MBytes)
The DRAM array can be configured with 256K x 36 1M x 36 and 4M x 36 SIMMs Each register defines an
address range that will cause a particular RAS line to be asserted (e g if the first DRAM row is 2 MBytes in
size then accesses within the 0 MByte–2 MBytes range will cause RAS0 to be asserted) The DRAM Row
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