82434LX Datasheet, PDF (42/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 5 PCISTS PCI STATUS REGISTER
Address Offset
Default Value
Attribute
Size
06 – 07h
40h
Read Only Read Write Clear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort PCI target abort and
DRAM or cache parity error PCISTS also indicates the DEVSEL timing that has been set by the PCMC
hardware Bits 15 12 are read write clear and bits 10 9 are read only
Bits Attribute
Description
15
RESERVED
14
R WC SIGNALED SYSTEM ERROR (SSE) When the PCMC asserts the SERR signal this bit
is also set to 1 Software sets SSE to 0 by writing a 1 to this bit
13
R WC RECEIVED MASTER ABORT STATUS (RMAS) When the PCMC terminates a Host-to-
PCI transaction (PCMC is a PCI master) which is not a special cycle with a master abort
this bit is set to 1 Software resets this bit to 0 by writing a 1 to it
12
R WC RECEIVED TARGET ABORT STATUS (RTAS) When a PCMC-initiated PCI transaction
is terminated with a target abort RTAS is set to 1 The PCMC also asserts SERR if the
SERR Target Abort bit in the ERRCMD Register is 1 Software resets RTAS to 0 by
writing a 1 to it
11
RESERVED
10 9 RO DEVSEL TIMING (DEVT) This 2-bit field indicates the timing of the DEVSEL signal
when the PCMC responds as a target The PCI specification defines three allowable
timings for assertion of DEVSEL 00^efast 01^emedium and 10^eslow (DEVT^e11 is
reserved) DEVT indicates the slowest time that a device asserts DEVSEL for any bus
command except configuration read and write cycles Note that these two bits determine
the slowest time that the PCMC asserts DEVSEL However the PCMC can also assert
DEVSEL in medium time
The PCMC asserts DEVSEL in response to sampling MEMCS asserted The PCMC
samples MEMCS one and two clocks after FRAME is asserted If MEMCS is
asserted one PCI clock after FRAME is asserted then the PCMC responds with
DEVSEL in slow time
8
R WC DATA PARITY DETECTED (DPD) This bit is set to 1 when all of the following conditions
are met 1) The PCMC asserted PERR or sampled PERR asserted 2) The PCMC
was the bus master for the operation in which the error occurred 3) The PERRE bit in
the Command Register is set to 1 Software resets DPD to 0 by writing a 1 to it
70
RESERVED
42