82434LX Datasheet, PDF (52/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Table 2 Attribute Definition
Read Write
Attribute
Definition
Read Only
Read cycles CPU cycles are serviced by the DRAM in a normal manner
Write cycles CPU initiated write cycles are ignored by the DRAM interface as well as the
cache Instead the cycles are passed to PCI for termination
Areas marked as Read Only are cacheable for Code accesses only These regions may be
cached in the second level cache however as noted above writes are forwarded to PCI
effectively write protecting the data
Write Only
Read cycles All read cycles are ignored by the DRAM interface as well as the second level
cache CPU-initiated read cycles are passed onto PCI for termination The write only state
can be used while copying the contents of a ROM accessible on PCI to main memory for
shadowing as in the case of BIOS shadowing
Write cycles CPU write cycles are serviced by the DRAM and cache in a normal manner
Read Write This is the normal operating mode of main memory Both read and write cycles from the CPU
and PCI are serviced by the DRAM and cache interface
Disabled
All read and write cycles to this area are ignored by the DRAM and cache interface These
cycles are forwarded to PCI for termination
Each PAM Register controls two regions typically 16-KByte in size Each of these regions have a 4-bit field
The four bits that control each region have the same encoding and are defined in Table 3
Table 3 Attribute Bit Assignment
Bits 7 3
Bits 6 2
Bits 5 1
Bits 4 0
Reserved Cache Enable Write Enable Read Enable
Description
x
x
0
0
DRAM Disabled Accesses Directed to PCI
x
0
0
1
Read Only DRAM Write Protected Non-
Cacheable
x
1
0
1
Read Only DRAM Write Protected
Cacheable for Code Accesses Only
x
0
1
0
Write Only
x
0
1
1
Read Write Non-Cacheable
x
1
1
1
Read Write Cacheable
NOTE
To enable PCI master access to the DRAM address space from C0000h to FFFFFh the MEMCS configuration registers of
the ISA or EISA bridge must be properly configured These registers must correspond to the PAM Registers in the PCMC
As an example consider a BIOS that is implemented on the expansion bus During the initialization process
the BIOS can be shadowed in main memory to increase the system performance When a BIOS is shadowed
in main memory it should be copied to the same address location To shadow the BIOS the attributes for that
address range should be set to write only The BIOS is shadowed by first doing a read of that address This
read is forwarded to the expansion bus The CPU then does a write of the same address which is directed to
main memory After the BIOS is shadowed the attributes for that memory area are set to read only so that all
writes are forwarded to the expansion bus
52