82434LX Datasheet, PDF (130/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 4 2 CAS -before-RAS Refresh Single
Figure 62 depicts a CAS -before-RAS refresh
cycle when the 82434NX is programmed for single
refresh cycles The diagram shows a write cycle
completing as the refresh timer inside the PCMC
generates a refresh request The cycle is less than a
Qword therefore a hidden refresh is not initiated
After the cycle completes all of the RAS and
CAS lines are negated The PCMC then asserts
CAS 7 0 and then sequentially asserts the RAS
lines starting with RAS1 since RAS0 was the
last RAS line asserted Each RAS line is assert-
ed for eight clocks
Figure 62 CAS -Before-RAS Refresh Single
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