82434LX Datasheet, PDF (18/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
BE 7 0
Type
Description
in BYTE ENABLES The byte enables indicate which byte lanes on the CPU data bus
carry valid data during the current bus cycle In the case of cacheable reads all 8 bytes
of data are driven to the Pentium processor regardless of the state of the byte enables
The byte enable signals indicate the type of special cycle when M IO ^eD C ^e0 and
W R ^e1 During special cycles only one byte enable is asserted by the CPU The
following table depicts the special cycle types and their byte enable encodings
Special Cycle Type
Shutdown
Flush
Halt Stop Grant
Write Back
Flush Acknowledge
Branch Trace Message
Asserted Byte Enable
BE0
BE1
BE2
BE3
BE4
BE5
ADS
When the PCMC decodes a Shutdown Special Cycle it asserts AHOLD drives
000 000 (the PCI Shutdown Special Cycle Encoding) on the A 31 0 lines and signals
the LBXs to latch the host address bus The PCMC then drives a Special Cycle on PCI
signaling the LBXs to drive the latched address (00 00) on the AD 31 0 lines during
the data phase The PCMC then asserts INIT for 16 HCLKs
In response to Flush and Flush Acknowledge Special Cycles the PCMC internally
inspects the Valid and Modified bits for each of the Second Level Cache Sectors If a
line is both valid and modified the PCMC drives the cache address of the line on the
A 18 7 and CAA CAB 6 3 lines and writes the line back to main memory The valid
and modified bits are both reset to 0 All valid and unmodified lines are simply marked
invalid
In response to a write back special cycle the PCMC simply returns BRDY to the CPU
The second level cache will be written back to main memory in response to the
following flush special cycle
If BE2 is asserted during a special cycle the 82434NX uses A4 to determine if the
cycle is a Halt or Stop Grant Special Cycle If A4^e0 the cycle is a Halt Special Cycle
and if A4^e1 the cycle is a Stop Grant Special cycle
In response to a halt special cycle the PCMC asserts AHOLD drives 000 001 (the PCI
halt special cycle encoding) on the A 31 0 lines and signals the LBXs to latch the host
address bus The PCMC then drives a special cycle on PCI signaling the LBXs to drive
the latched address (00 01) on the AD 31 0 lines during the data phase
When the 82434NX PCMC detects a CPU Stop Grant Special Cycle (M IO ^e0
D C ^e0 W R ^e1 A4^e1 BE 7 0 ^eFBh) it generates a PCI Stop Grant Special
cycle with 0002h in the message field (AD 15 0 ) and 0012h in the message dependent
data field (AD 31 16 ) during the first data phase (IRDY asserted)
in ADDRESS STROBE The Pentium processor asserts ADS to indicate that a new bus
cycle is beginning ADS is driven active in the same clock as the address byte enable
and cycle definition signals The PCMC ignores a floating low ADS that may occur
when BOFF is asserted as the CPU is asserting ADS
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