82434LX Datasheet, PDF (59/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Bits
Description
7 SERR ON RECEIVED TARGET ABORT When this bit is set to 1 (and bit 8 of the PCICMD
Register is 1) the PCMC asserts SERR upon receiving a target abort When this bit is set to 0 the
PCMC is disabled from asserting SERR upon receiving a target abort
6 SERR ON TRANSMITTED PCI DATA PARITY ERROR When this bit is set to 1 (and bits 6 and 8
of the PCICMD Register are both 1) the PCMC asserts SERR when it detects a data parity error as
a result of a CPU-to-PCI write (PERR detected asserted) When this bit is set to 0 the PCMC is
disabled from asserting SERR when data parity errors are detected via PERR
5 82434LX RESERVED
82434NX SERR ON RECEIVED PCI DATA PARITY ERROR When this bit is set to 1 (and bits 6
and 8 of the PCICMD Register are both 1) the PCMC asserts SERR when it detects a data parity
error as a result of a CPU-to-PCI read (PAR incorrect with received data) In this case the SERR
signal is asserted when parity errors are detected on PCI return data When this bit is set to 0 the
PCMC is disabled from asserting SERR when data parity errors are detected during a CPU-to-PCI
read
4 82434LX RESERVED
82434NX SERR ON PCI ADDRESS PARITY ERROR When this bit is set to 1 (and bits 6 and 8 of
the PCICMD Register are both 1) the PCMC asserts SERR when it detects an address parity error
on PCI transactions When this bit is set to 0 the PCMC is disabled from asserting SERR when
address parity errors are detected on PCI transactions
3 82434LX RESERVED
82434NX PERR ON RECEIVING A DATA PARITY ERROR This bit indicates whether the
PERR signal is implemented in the system When this bit is set to 1 (and bit 6 of the PCICMD
Register is 1) the PCMC asserts PERR when it detects a data parity error (PAR incorrect with
received data) either from a CPU-to-PCI read or a PCI master write to memory When this bit is set to
0 (or bit 6 of the PCICMD Register is set to 0) the PERR signal is not asserted by the PCMC
2 L2 CACHE PARITY ENABLE This bit indicates that the second level cache implements parity When
this bit is set to 1 bits 0 and 1 of this register control the checking of parity errors during CPU reads
from the second level cache If this bit is 0 parity is not checked when the CPU reads from the
second level cache (PCHK ignored) and neither bit 1 nor bit 0 apply
1 SERR ON DRAM L2 CACHE DATA PARITY ERROR ENABLE This bit enables disables the
SERR signal for parity errors on reads from main memory or the second level cache When this bit
is set to 1 and bit 0 of this register is set to 1 (and bits 6 and 8 of the PCICMD Register are set to 1)
SERR is enabled upon a PCHK assertion from the CPU when reading from main memory or the
second level cache The processor indicates that a parity error was received by asserting PCHK
The PCMC then latches status information in the Error Status Register and asserts SERR When
this bit is 0 SERR is not asserted upon detecting a parity error Bits 1 0 ^e10 is a reserved
combination
0^eDisable assertion of SERR upon detecting a DRAM second level cache read parity error
1^eEnable assertion of SERR upon detecting a DRAM second level cache read parity error
0 MCHK ON DRAM L2 CACHE DATA PARITY ERROR ENABLE When this bit is set to 1 PEN is
asserted for data returned from main memory or the second level cache The processor indicates
that a parity error was received by asserting the PCHK signal In addition the processor invokes a
machine check exception if enabled via the MCE bit in CR4 in the Pentium processor The PCMC
then latches status information in the Error Status register When this bit is 0 PEN is not asserted
Bits 1 0 ^e10 is a reserved combination
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