82434LX Datasheet, PDF (135/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 3 2 CPU READ FROM PCMC INTERNAL
REGISTER
A read from an internal PCMC register (either CSE
Register TRC Register or a configuration space-
mapped register) is shown in Figure 66 The I O
read cycle is from either CF8h to access the CSE
register CF9h to access the TRC Register or C0XXh
when configuration space is enabled to access a
configuration space-mapped register The PCMC
decodes the cycle and asserts AHOLD to tri-state
the CPU address lines The PCMC then drives the
contents of the addressed register onto the A 31 0
lines One byte is enabled on each rising HCLK edge
for four consecutive clocks The PCMC signals the
LBXs that the current cycle is a read from an internal
PCMC register by issuing the ADCPY command to
the LBXs over the HIG 4 0 lines The LBXs sample
the HIG 4 0 command and copy the address lines
onto the data lines Finally the PCMC negates
AHOLD and asserts BRDY terminating the cycle
Figure 66 CPU Read from PCMC Configuration Register
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