82434LX Datasheet, PDF (143/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 4 2 PCI MASTER READ FROM MAIN MEMORY
Figure 71 depicts a PCI master read from main
memory The PCI master initiates the cycle by driv-
ing the read address on the AD 31 0 lines and as-
serting FRAME The PCMC drives the LPMA com-
mand on the PIG 3 0 lines causing the LBXs to re-
tain the address latched on the previous PCLK rising
edge The PCMC drives the DPRA command on the
HIG 4 0 lines enabling the LBXs to drive the read
address onto the host address lines The snoop cy-
cle misses in the second level cache and either hits
an unmodified line or misses in the first level cache
The cycle is then forwarded to the DRAM interface
A read of four Qwords is performed Each Qword is
posted in the PCI-Memory Read Prefetch Buffer
The data is then driven onto PCI in an eight Dword
burst cycle If the master terminates the cycle before
sampling STOP then IRDY STOP and
DEVSEL are all negated after FRAME is sam-
pled inactive If the master intended to continue
bursting then the master negates FRAME when it
samples STOP asserted and IRDY STOP and
DEVSEL are negated one clock later
Figure 71 PCI Master Read from Main Memory-Page Hit
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