82434LX Datasheet, PDF (110/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 4 2 Read Page Miss
Figure 45 depicts a CPU burst read page miss from
DRAM The 82434LX decodes the CPU address as
a page miss and switches from initially driving the
column address to driving the row address on the
MA 10 0 lines RAS is then negated to precharge
the DRAMs and then asserted to cause the DRAMs
to latch the new row address The PCMC then
switches the MA 10 0 lines to drive the column ad-
dress and asserts CAS 7 0 CMR (CPU Memory
Read) is driven on the HIG 4 0 lines to enable the
memory data to host data path through the LBXs
The PCMC advances the MA 1 0 lines through the
Pentium processor burst order negating and assert-
ing CAS 7 0 to read each Qword The host data is
latched on the falling edge of MDLE when
CAS 7 0 are negated The latch is opened again
when MDLE is sampled asserted by the LBXs The
LBXs tri-state the host data bus when HIG 4 0
change to NOPC and MDLE rises A single read
page miss from DRAM is similar to the first read of
this sequence The HIG 4 0 lines are driven to
NOPC when BRDY is asserted
Figure 45 DRAM Read Cycle-Page Miss
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