82434LX Datasheet, PDF (41/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 4 PCICMD PCI COMMAND REGISTER
Address Offset
Default
Attribute
Size
04 – 05h
06h
Read Write
16 bits
This 16-bit register provides basic control over the PCMC’s ability to respond to PCI cycles The PCICMD
Register enables and disables the SERR signal the parity error signal (PERR ) PCMC response to PCI
special cycles and enables and disables PCI master accesses to main memory
Bits
Description
15 9 RESERVED
8 SERR ENABLE (SERRE) SERRE enables disables the SERR signal When SERRE^e1 and
PERRE^e1 SERR is asserted if the PCMC detects a PCI Bus address data parity error or main
memory (DRAM) or cache parity error and the corresponding errors are enabled in the Error-
Command Register When SERRE^e1 and bit 7 in the Error Command Register is set to 1 the PCMC
asserts SERR when it detects a target abort on a PCMC-initiated PCI cycle When SERRE^e0
SERR is never asserted
7 RESERVED
6 PARITY ERROR ENABLE (PERRE) PERRE controls the PCMC’s response to PCI parity errors This
bit is a master enable for bit 3 of the ERRCMD Register PERRE works in conjunction with the
SERRE bit to enable SERR assertion when the PCMC detects a PCI bus parity error or a main
memory or cache parity error
5 3 RESERVED
2 BUS MASTER ENABLE (BME) The PCMC does not support disabling of its bus master capability on
the PCI Bus This bit is always set to 1 permitting the PCMC to function as a PCI Bus master Writes
to this bit position have no affect
1 MEMORY ACCESS ENABLE (MAE) This bit enables disables PCI master access to main memory
(DRAM) When MAE^e1 the PCMC permits PCI masters to access main memory if the MEMCS
signal is asserted When MAE^e0 the PCMC does not respond to PCI master main memory
accesses (MEMCS asserted)
0 I O ACCESS ENABLE (IOAE) The PCMC does not respond to PCI I O cycles hence this command
is not supported PCI master access to I O space on the Host Bus is always disabled
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