82434LX Datasheet, PDF (88/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
5 1 3 3 Cache Line Fill (82434LX)
If the CPU issues a memory read cycle to cacheable
memory which does not hit in the second level
cache a cache line fill occurs Figure 32 depicts a
first and second level cache line fill with burst
SRAMs
Figure 33 depicts a CPU read cycle which forces a
write-back in the second level cache
290479 – 34
Figure 32 Cache Line Fill with Burst SRAM DRAM Page Hit 7-4-4-4 Timing (82434LX)
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