82434LX Datasheet, PDF (190/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
11 0 TESTABILITY
A NAND tree is provided in the 82434LX and
82434NX PCMCs for Automated Test Equipment
(ATE) board level testing The NAND tree allows the
tester to test the connectivity of a subset of the
PCMC signal pins
For the 82434LX the output of the NAND tree is
driven on pin 109 The NAND tree is enabled when
A24^e1 A25^e0 A26^e1 and TESTEN^e1 at the
rising edge of PWROK PLL Bypass mode is en-
abled when A24^e1 and TESTEN^e1 at the rising
edge of PWROK In PLL Bypass mode the 82434LX
and 82434NX PCMC AC specifications are affected
as follows
1 Output valid delays increase by 20 ns
2 All hold times are 20 ns
3 Setup times and propagation delays are
unaffected
4 Input clock high and low times are 100 ns
In both the NAND tree test mode and PLL Bypass
mode TESTEN must remain asserted throughout
the testing A 28 24 should be set up at least
1 HCLK before the rising edge of PWROK and held
at least 3 HCLKs after PWROK Table 11 shows the
order of the NAND tree inside the PCMC
When not in NAND Tree test mode the 82434LX
drives the output of the host clock PLL onto pin 109
82434NX Test Modes
The state of A 28 24 TESTEN CPURST and
PWROK can place the 82434NX PCMC into two test
modes When PWROK is low A 27 24 and
TESTEN directly control the mode of operation of
the PCMC When PWROK is high the state of
A 27 24 and TESTEN are latched and the PCMC
remains in the indicated mode until PWROK is again
negated The high order LBX samples the state of
A27 on the falling edge of CPURST
When PWROK is low and both TESTEN and A27
are low the 82434NX drives MA11 onto pin 109 If
both TESTEN and A27 are low when PWROK tran-
sitions from low to high the PCMC continues to
drive MA11 onto pin 109 If the high order LBX sam-
ples A27 low on the falling edge of CPURST it will
tri-state pin 123
When PWROK is low TESTEN is low and A27 is
high the PCMC drives the output of the host clock
PLL onto pin 109 Observing pin 109 when in this
mode indicates if the host clock PLL has locked
onto the correct frequency If TESTEN is low and
A27 is high when PWROK transitions from low to
high the PCMC continues to drive the output of the
host clock PLL onto pin 109 regardless of the val-
ues of TESTEN and A27 If the high order LBX sam-
ples A27 high on the falling edge of CPURST it
drives the output of its host clock PLL onto pin 123
No phase delay information can be inferred from
these outputs
When PWROK is low TESTEN is high A26 is high
A25 is low A28 is high and A24 is high the PCMC
will drive the output of the NAND tree onto pin 109 If
TESTEN is high A26 is high and A25 is low when
PWROK transitions from low to high the PCMC con-
tinues to drive the output of the NAND tree onto
pin 109
A27 must be pulled low via a pulldown resistor to
ground for normal operation
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