82434LX Datasheet, PDF (164/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
9 5 12 SECOND LEVEL CACHE BURST SRAM TIMING 60 MHz (82434LX)
Symbol
Functional Operating Range (V_CC ^e 4 75V to 5 25V T_CASE ^e 0 C to ^a85 C)
Parameter
Min Max Fig Notes
t30a
CAA 6 3 CAB 6 3 Propagation Delay from A 6 3
0 8 5 77 0 pF
t30b
CAA 6 3 CAB 6 3 Valid Delay from HCLKIN Rising
0 8 2 78 0 pF
t31
CADS 1 0 Valid Delay from HCLKIN Rising
1 5 8 2 78 0 pF
t32
CADV 1 0 Valid Delay from HCLKIN Rising
1 5 8 2 78 0 pF
t33
CWE 7 0 Valid Delay from HCLKIN Rising
1 0 10 5 78 0 pF
t34a
COE 1 0 Falling Edge Valid Delay from HCLKIN Rising
0 9 5 78 0 pF
t34b
COE 1 0 Rising Edge Valid Delay from HCLKIN Rising
0 6 0 78 0 pF
t35
CALE Valid Delay from HCLKIN Rising
0 8 5 78 0 pF
9 5 13 DRAM INTERFACE TIMING 60 MHz (82434LX)
Symbol
Functional Operating Range (V_CC ^e 4 75V to 5 25V T_CASE ^e 0 C to ^a85 C)
Parameter
Min
Max Fig
Notes
t40a
RAS 5 0 Valid Delay from
HCLKIN Rising
0
8 0 78 50 pF
t40b
RAS 5 0 Pulse Width High
4 HCLKs^b5
84 RAS precharge at beginning
of page miss cycle 50 pF
t41a
CAS 7 0 Valid Delay from
HCLKIN Rising
0
8 0 78 50 pF
t41b
CAS 7 0 Pulse Width High
1 HCLK^b5
84 CAS precharge during burst
cycles 50 pF
t42
WE Valid Delay from HCLKIN
Rising
0
21 78 50 pF
t43a
MA 10 0 Propagation Delay from
A 23 3
0
23 77 50 pF
t43b
MA 10 0 Valid Delay from HCLKIN
Rising
0
10 7 78 50 pF
164