82434LX Datasheet, PDF (167/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
9 6 82434NX AC Characteristics
The AC characteristics given in this section consist of propagation delays valid delays input setup require-
ments input hold requirements output float delays output enable delays output-to-output delays pulse
widths clock high and low times and clock period specifications Figure 77 through Figure 85 define these
specifications Output test loads are listed in the right column
In Figure 77 through Figure 85 VT ^e 1 5V for the following signals
A 31 0 BE 7 0 PEN D C W R M IO HLOCK ADS PCHK HITM EADS BRDY
BOFF AHOLD NA KEN INV CACHE SMIACT INIT CPURST CALE CADV 1 0 COE 1 0
CWE 7 0 CADS 1 0 CAA 6 3 CAB 6 3 WE RAS 5 0 CAS 7 0 MA 10 0 C BE 3 0
FRAME TRDY IRDY STOP PLOCK GNT DEVSEL MEMREQ PAR PERR SERR
REQ MEMCS FLSHBUF MEMACK PWROK HCLKIN HCLKA – HCLKF PCLKIN PCLKOUT
VT ^e 2 5V for the following signals
PPOUT 1 0 EOL HIG 4 0 PIG 3 0 MIG 2 0 DRVPCI MDLE PCIRST
9 6 1 HOST CLOCK TIMING 66 MHz (82434NX) PRELIMINARY
Functional Operating Range (V_CC ^e 4 75V to 5 25V V_CC3 ^e 3 135V to 3 465V T_CASE ^e 0 C to ^a85 C)
Symbol
Parameter
Min
Max
Fig
Notes
t1a
HCLKOSC High Time
60
82
t1b
HCLKOSC Low Time
50
82
t2a
HCLKIN Period
15
20
82
t2b
HCLKIN Period Stability
g100
ps⁽¹⁾
t2c
HCLKIN High Time
4
82
t2d
HCLKIN Low Time
4
82
t2e
HCLKIN Rise Time
15
83
t2f
HCLKIN Fall Time
15
83
t3a
HCLKA–HCLKF Output-to-Output Skew
05
85
0 pF
t3b
HCLKA–HCLKF High Time
50
82
0 pF
t3c
HCLKA–HCLKF Low Time
50
82
0 pF
NOTES
1 Measured on rising edge of adjacent clocks at 1 5V
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