82434LX Datasheet, PDF (62/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
NOTE
Memory that is disabled by the gap created by this register is remapped to the top of memory This
remapped memory is accessible except in the case where this would cause the top of main memory
to exceed 192 MBytes (or 512 MBytes for the 82434NX)
Bits
Description
15 MEMORY SPACE GAP ENABLE (MSGE) MSGE enables and disables the memory space gap
When MSGE is set to 1 the CPU accesses to the address range defined by this register are
forwarded to PCI bus The size of the gap created in main memory causes a corresponding amount
of DRAM to be remapped at the top of main memory (top specified by DRB Registers) If the Frame
Buffer Range is programmed below 16 MBytes and within main memory space the MSG register
must include the Frame Buffer Range When MSGE is reset to 0 the memory space gap is disabled
14 12
MEMORY SPACE GAP SIZE (MSGS) This 3 bit field defines the size of the memory space gap If
the Frame Buffer Range is programmed below 16 MBytes and within main memory space this
register must include the frame buffer range The amount of main memory specified by these bits is
remapped to the top of main memory
Bit 14 12
000
001
011
111
Memory Gap Size
1 MByte
2 MBytes
4 MBytes
8 MBytes
NOTE
All other combinations are reserved
11 8 RESERVED
7 4 MEMORY SPACE GAP STARTING ADDRESS (MSGSA) These 4 bits define the starting address
of the memory space gap in the space from 1 MByte – 16 MBytes These bits are compared against
A 23 20 The memory space gap starting address must be a multiple of the memory space gap
size For example a 2 MBytes gap must start at 2 4 6 8 10 12 or 14 MBytes
3 0 RESERVED
3 2 26 FBR FRAME BUFFER RANGE REGISTER
Address Offset
Default Value
Attribute
Size
7C-7Fh
0000h
Read Write
32 bits
This 32-bit register enables and disables a frame buffer area and provides attribute settings for the frame
buffer area The attributes defined in this register are intended to increase the performance of the frame buffer
The FBR Register can be used to accommodate PCI devices that have their memory mapped onto PCI from
the top of main memory to 4 GByte–512-KByte range (e g a linear frame buffer) If the Frame Buffer Range is
located within the 1 MByte–16 MBytes main memory region where DRAM is populated the Memory Space
Gap Register must be programmed to include the Frame Buffer Range
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