82434LX Datasheet, PDF (65/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
However PCI masters can access SMRAM when
the top of memory is selected
When the 82434NX PCMC detects a CPU stop grant
special cycle (M IO ^e0 D C ^e0 W R ^e1
A4^e1 BE 7 0 ^eFBh) it generates a PCI Stop
Grant Special cycle with 0002h in the message field
(AD 15 0 ) and 0012h in the message dependent
data field (AD 31 16 ) during the first data phase
(IRDY asserted)
4 3 PC Compatibility Range
The PC Compatibility Range is the first MByte of the
Memory Map The 512 KByte–1 MByte range is sub-
divided into several regions as shown in Figure 10
Each region is provided with programmable attri-
butes in the PAM Registers The attributes are Read
Enable (RE) Write Enable (WE) and Cache Enable
(CE) The attributes determine readability writeabili-
ty and cacheability of the corresponding memory re-
gion When the associated bit in the PAM Register is
set to a 1 the attribute is enabled and when set to a
0 the attribute is disabled The following rules apply
for cacheability in the first level and second level
caches
1 If RE^e1 WE^e1 and CE^e1 the region is
cacheable in the first level and second level
caches
2 If RE^e1 WE^e0 and CE^e1 the region is
cacheable only on code reads (i e D C ^e0)
Data reads do not result in a line fill Writes to the
region are not serviced by the secondary cache
but are forwarded to PCI
Figure 10 CPU Memory Address Map PC Compatibility Range
290479 – 12
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