82434LX Datasheet, PDF (97/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
290479 – 39
Figure 37 Snoop Hit to Modified Line in First Level Cache Write-Back from First Level Cache to
Second Level Cache and Send to PCI
This cycle is shown for the case of a second level
cache with burst SRAMs In this case as it com-
pletes the second level cache tag lookup the PCMC
samples HITM active The write-back is written to
the second level cache and simultaneously stored in
the memory to PCI prefetch buffer In the case
shown in Figure 33 the PCI master requests a data
item which is contained in Qword 0 of the cache line
Note that a write-back from the first level cache al-
ways starts with Qword 0 and finishes with Qword 3
Thus the HIG 4 0 lines are sequenced through the
following order SWB0 SWB1 SWB2 SWB3 If the
PCI master requests a data item which is contained
in Qword 1 the HIG 4 0 lines sequence through the
following order NOPC SWB0 SWB1 SWB2 If the
PCI master requests a data item which is contained
in Qword 2 the HIG 4 0 lines sequence through the
following order NOPC NOPC SWB0 SWB1 If the
PCI master requests a data item which is contained
in Qword 3 the HIG 4 0 lines sequence through the
following order NOPC NOPC NOPC SWB0
AHOLD is negated after the write-back cycle is com-
plete
If the CPU has begun a read cycle directed to PCI
and the snoop results in a hit to a modified line in the
first level cache BOFF is asserted for one clock to
abort the CPU read cycle and re-order the write-
back cycle before the pending read cycle
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