82434LX Datasheet, PDF (127/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 3 5 Burst DRAM Write Page Miss
Figure 59 depicts a CPU burst write page miss to
DRAM The 82434NX decodes the CPU write cycle
as a DRAM page miss and drives the PCMWQ com-
mand HIG 4 0 lines to post the write data to the
LBXs In the figure the write cycle is posted to the
CPU-to-Memory Posted Write Buffer at 3-1-1-1
When the cycle is decoded as a page miss the
PCMC switches the MA 11 0 lines from the column
address to the row address and asserts WE in
clock 4 The PCMC drives the RCMWQ command
on MIG 2 0 to enable the LBXs to drive the first
Qword of the write onto the memory data lines
MEMDRV is then driven to cause the LBXs to con-
tinue to drive the first Qword The RAS signal for
the currently decoded row is negated to precharge
the DRAMs RAS is then asserted to cause the
DRAMs to latch the row address The PCMC then
switches the MA 11 0 lines to the column address
and asserts CAS 7 0 to initiate the first write
CAS 7 0 are then negated and asserted to per-
form the writes to the DRAMs as the MA 1 0 lines
advance through the Pentium processor burst order
A single write is similar to the first write of the burst
sequence The MIG 2 0 lines are driven to NOPM in
the clock when the last CAS 7 0 are asserted
Figure 59 Burst DRAM Write Cycle-Page Miss
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