82434LX Datasheet, PDF (85/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
The cycle begins with the CPU driving address and
status onto Host Bus and asserting ADS The
PCMC asserts CADS and COE in the second
clock After the address is latched by the burst
SRAMs and the PCMC determines that no write-
back cycles are required from the second level
cache CALE is negated Back-to-back burst reads
from the second level cache are shown in Figure 29
When the Secondary Cache Allocation (SCA) bit in
the Secondary Cache Control Register is set to 1
the PCMC performs a line fill in the secondary
cache even if the CACHE signal from the CPU is
negated In this case AHOLD is asserted to prevent
the CPU from beginning a new cycle while the sec-
ond level cache line fill is completing
Back-to-back burst reads which hit in the second
level cache complete at a rate of 3-1-1-1 1-1-1-1
with burst SRAMs As the last BRDY is being re-
turned to the CPU the PCMC asserts CADS caus-
ing the SRAMs to latch the new address This allows
the data for the second cycle to be transferred to the
CPU on the clock after the first cycle completes
290479 – 31
Figure 29 Pipelined Back-to-Back Burst Reads from Second Level Cache (82434LX)
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