82434LX Datasheet, PDF (47/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Bits
Description
5 SRAM TYPE (SRAMT) This bit selects between standard SRAMs or burst SRAMS to implement the
second level cache When SRAMT^e0 standard SRAMs are selected When SRAMT^e1 burst
SRAMs are selected This bit reflects the signal level on the A29 pin at the rising edge of the PWROK
signal This value can be overwritten with subsequent writes to the SCC Register
4 82434LX SECONDARY CACHE ALLOCATION (SCA) SCA controls when the PCMC performs line
fills in the second level cache When SCA is set to 0 only CPU reads of cacheable main memory with
CACHE asserted are cached in the second level cache When SCA is set to 1 all CPU reads of
cacheable main memory are cached in the second level cache
3 CACHE BYTE CONTROL (CBC) When programmed for asynchronous SRAMs this bit defines
whether the cache uses individual write enables per byte or has a single write enable and byte select
lines per byte When CBC is set to 1 write enable control is used When CBC is set to 0 byte select
control is used
2 82434LX RESERVED
82434NX SRAM CONNECTIVITY (SRAMC) This bit enables different connectivities for the second
level cache When SRAMC is set to 0 the second level cache is in 82434LX compatible mode and all
connections between the PCMC and second level cache SRAMs are the same as the 82434LX
When asynchronous SRAMs are used setting this bit to 1 enables the CCS 1 0 functionality
CCS 1 0 are used with asynchronous SRAMs to de-select the SRAMs placing them in a low
power standby mode When the CPU runs a halt or stop grant special cycle the 82434NX negates
CCS 1 0 placing the second level cache in a power saving mode The PCMC then asserts
CCS 1 0 (activating the SRAMs) when the CPU asserts ADS When using burst SRAMs setting
this bit to 1 enables the CCS1 functionality and indicates to the PCMC that no external address
latch is present
1 82434LX SECONDARY CACHE WRITE POLICY (SCWP) SCWP selects between write-back and
write-through cache policies for the second level cache When SCWP^e0 and the second level cache
is enabled (bit 0^e1) the second level cache is configured for write-through mode When SCWP^e1
and the second level cache is enabled (bit 0^e1) the second level cache is configured for write-back
mode
82434NX RESERVED Secondary cache write-through mode is not supported The secondary cache
is always in write-back mode and this bit has no affect SCWP can be set to 0 however the 82434NX
will still operate the secondary cache in write-back mode
0 SECONDARY CACHE ENABLE (SCE) SCE enables and disables the secondary cache When
SCE^e1 the secondary cache is enabled When SCE^e0 the secondary cache is disabled When the
secondary cache is disabled the PCMC forwards all main memory cycles to the DRAM interface
Note that setting this bit to 0 does not affect existing valid cache lines If a cache line contains
modified data the data is not written back to memory Valid lines in the cache remain valid When the
secondary cache is disabled the CWE 7 0 lines remain negated COE 1 0 may still toggle
When system software disables secondary caching through this register during run-time the software
should first flush the second level cache This process is accomplished by first disabling first level
caching via the PCE bit in the HCS Register This prevents the KEN signal from being asserted
which disables any further line fills At this point software executes the WBINVD instruction to flush
the caches When the instruction completes bit 0 of this register can be reset to 0 disabling the
secondary cache The first level cache can then be enabled by writing the PCE bit in the HCS
Register
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