82434LX Datasheet, PDF (27/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
PERR
SERR
Type
Description
sts
PARITY ERROR PERR may be pulsed by any agent that detects a parity error during
an address phase or by the master or the selected target during any data phase in which
the AD lines are inputs The PERR signal is enabled when the PERR on Receiving
Data Parity Error bit in the Error Command Register (offset 70h) and the Parity Error
Enable bit in the PCI Command Register (offset 04h) are both set to 1
When enabled CPU-to-PCI write data is checked for parity errors by sampling the
PERR signal two PCI clocks after data is driven Also when enabled PERR is
asserted by the PCMC when it detects a data parity error on CPU read data from PCI and
PCI master write data to main memory PERR is neither sampled nor driven by the
PCMC when either the PERR on Receiving Data Parity Error bit in the Error Command
Register or the Parity Error Enable bit in the PCI Command Register is reset to 0
o d SYSTEM ERROR SERR may be pulsed by any agent for reporting errors other than
parity SERR is asserted by the PCMC whenever a serious system error (not
necessarily a PCI error) occurs The intent is to have the PCI central agent (for example
the expansion bus bridge) assert NMI to the processor Control over the SERR signal is
provided via the Error Command Register (offset 70h) when the Parity Error Enable bit in
the PCI Command Register (offset 04h) is set to 1 When the SERR DRAM L2 Cache
Data Parity Error bit is set to 1 SERR is asserted upon detecting a parity error on CPU
read cycles from DRAM If the L2 Cache Parity bit is also set to 1 SERR will be
asserted upon detecting a parity error on CPU read cycles from the second level cache
The Pentium processor indicates these parity errors to the PCMC via the PCHK signal
When the SERR on PCI Address Parity Error bit is set to 1 the PCMC asserts SERR if
a parity error is detected during the address phase of a PCI master cycle
When the SERR on Received PCI Data Parity bit is set to 1 the PCMC asserts SERR
if a parity error is detected on PCI during a CPU read from PCI During CPU to PCI write
cycles when the SERR on Transmitted PCI Data Parity Error bit is set to 1 the PCMC
asserts SERR in response to sampling PERR active When the SERR on Received
Target Abort bit is set to 1 the PCMC asserts SERR when the PCMC receives a target
abort on a PCMC initiated PCI cycle If the Parity Error Enable bit in the PCI Command
Register is reset to 0 SERR is disabled and is never asserted by the PCMC
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