82434LX Datasheet, PDF (173/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Symbol
Functional Operating Range (V_CC ^e 4 75V to 5 25V V_CC3 ^e 3 135V to 3 465V
T_CASE ^e 0 C to ^a85 C) (Continued)
Parameter
Min Max Fig
Notes
t63a
GNT Setup Time to PCLKIN Rising
10
79
t63b
GNT Hold Time from PCLKIN Rising
0
79
t64a
MEMCS Setup Time to PCLKIN Rising 7
79
t64b
MEMCS Hold Time from PCLKIN Rising 0
79
t65
PCIRST Low Pulse Width
1 ms
84 Hard Reset via TRC Register 0 pF
9 6 8 LBX INTERFACE TIMING 66 MHz (82434NX) PRELIMINARY
Functional Operating Range (V_CC ^e 4 75V to 5 25V V_CC3 ^e 3 135V to 3 465V T_CASE ^e 0 C to ^a85 C)
Symbol
Parameter
Min Max Fig Notes
t70
HIG 4 0 Valid Delay from HCLKIN Rising
08
65
78
0 pF
t71
MIG 2 0 Valid Delay from HCLKIN Rising
09
65
78
0 pF
t72
PIG 3 0 Valid Delay from PCLKIN Rising
15
12
78
0 pF
t73
PCIDRV Valid Delay from PCLKIN Rising
1
13
78
0 pF
t74a
MDLE Falling Edge Valid Delay from HCLKIN Rising 0 6
60
78
0 pF
t74b
MDLE Rising Edge Valid from HCLKIN Rising
06
60
85
0 pF
t75a
EOL PPOUT 1 0 Setup Time to PCLKIN Rising
77
79
t75b
EOL PPOUT 1 0 Hold Time from PCLKIN Rising
10
79
9 6 9 HOST CLOCK TIMING 50 and 60 MHz (82434NX)
Functional Operating Range (V_CC ^e 4 75V to 5 25V V_CC3 ^e 3 135V to 3 465V T_CASE ^e 0 C to ^a85 C)
Symbol
Parameter
Min
Max
Fig
Notes
t1a
HCLKOSC High Time
60
82
t1b
HCLKOSC Low Time
50
82
t2a
HCLKIN Period
16 66
20
82
t2b
HCLKIN Period Stability
g100
ps⁽¹⁾
t2c
HCLKIN High Time
4
82
t2d
HCLKIN Low Time
4
82
t2e
HCLKIN Rise Time
15
83
t2f
HCLKIN Fall Time
15
83
t3a
HCLKA–HCLKF Output-to-Output Skew
05
85
0 pF
t3b
HCLKA–HCLKF High Time
50
82
0 pF
t3c
HCLKA–HCLKF Low Time
50
82
0 pF
NOTES
1 Measured on rising edge of adjacent clocks at 1 5V
173