82434LX Datasheet, PDF (96/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
ter requests a data item that hits Qword 1 the SWB0
command is sent via the HIG 4 0 lines to store
Qword 1in the first buffer location The next read
from the cache is not in ascending order thus a
NOPC is sent on the HIG 4 0 lines This Qword is
not posted in the buffer The next read from the
cache is to Qword 3 SWB2 is sent on the HIG 4 0
lines The final read from the cache is Qword 2
SWB1 is sent on the HIG 4 0 lines Thus Qword 1
is placed in entry 0 in the buffer Qword 2 is placed
in entry 1 in the buffer and Qword 3 is placed in entry
2 in the buffer The ordering between the Qwords
read from the cache and the HIG 4 0 commands
when using burst SRAMs is summarized in Table 9
Table 9 HIG 4 0 Command Sequence for
Second Level Cache to PCI Master Read
Prefetch Buffer Transfer
Burst Order
from Cache
HIG 4 0 Command
Sequence
0123
SWB0 SWB1
SWB2 SWB3
1032
SWB0 NOPC
SWB2 SWB1
2301
SWB0 SWB1
NOPC NOPC
3210
SWB0 NOPC
NOPC NOPC
When using standard asynchronous SRAMs the
read from the SRAMs occurs in a linear burst order
Thus CAA 4 3 and CAB 4 3 count in a linear burst
order and the Store Write Buffer commands are sent
in linear order The burst ends at the cache line
boundary and does not wrap around and continue
with the beginning of the cache line
A PCI master write cycle which hits a modified line in
the second level cache and either hits an unmodified
line in the first level cache or misses in the first level
cache will also cause a transfer from the second
level cache to the LBXs In this case the read from
the SRAMs is posted to main memory and the line is
invalidated in the second level cache The cycle
would differ only slightly from the above cycle INV
would be asserted with EADS Instead of the
DPRA command the PCMC would use the DPWA
command to drive the snoop address onto the host
address bus The write would be posted to the
DRAM thus the PCMC would drive the PCMWQ
command on the HIG 4 0 lines to post the write to
DRAM
A snoop cycle can result in a write-back from the
first level cache to both the second level and LBXs
in the case of a PCI master read cycle which hits a
modified line in the first level cache and hits either a
modified or unmodified line in the second level
cache The line is written to both the second level
cache and the memory to PCI read prefetch buffer
The cycle is shown in Figure 37
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