82434LX Datasheet, PDF (55/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Boundary (DRB) Registers are programmed with an 8-bit upper address limit value This upper address limit is
compared to A 27 20 of the Host address bus for each row to determine if DRAM is being targeted Since
this value is 8 bits and the resolution is 1 MByte the total bits compared span a 256 MByte space However
only 192 MBytes of main memory is supported
Bits
Description
7 0 ROW BOUNDARY ADDRESS IN MBYTES This 8-bit value is compared against address lines
A 27 20 to determine the upper address limit of a particular row i e DRB ^b previous DRB ^e row
size
Row Boundary Address in MBytes
These 8-bit values represent the upper address limits of the six rows (i e this row - previous row ^e row size)
Unpopulated rows have a value equal to the previous row (row size ^e 0) The value programmed into DRB5
reflects the maximum amount of DRAM in the system Memory remapped at the top of DRAM as a result of
setting the Memory Space Gap Register is not reflected in the DRB Registers The top of memory is always
determined by the value written into DRB5 added to the memory space gap size (if enabled)
As an example of a general purpose configuration where 3 physical rows are configured for either single-sided
or double-sided SIMMs the memory array would be configured like the one shown in Figure 8 In this configu-
ration the PCMC drives two RAS signals directly to the SIMM rows If single-sided SIMMs are populated the
even RAS signal is used and the odd RAS is not connected If double-sided SIMMs are used both RAS
signals are used
Figure 8 SIMMs and Corresponding DRB Registers
290479 – 9
The following 2 examples describe how the DRB Registers are programmed for cases of single-sided and
double-sided SIMMs on a motherboard having a total of 6 SIMM sockets
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