82434LX Datasheet, PDF (57/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Bits
Description
7 0 ROW BOUNDARY ADDRESS IN MBYTES This 8-bit value is concatenated with a nibble from the
DRBE Register and then compared against address lines A 29 20 to determine the upper address
limit of a particular row (i e DRB ^b previous DRB ^e row size)
Row Boundary Address in MBytes
These 10-bit values represent the upper address limits of the 8 rows (i e this row - previous row ^e row size)
Unpopulated rows have a value equal to the previous row (row size ^e 0) The value programmed into
ll ^{DRBE 31 28 DRB7 reflects the maximum amount of DRAM in the system Memory remapped at the top of}
DRAM as a result of setting the Memory Space Gap Register is not reflected in the DRB Registers The top of
ll ^{memory is determined by the value written into DRBE 31 28 DRB7 added to the memory space gap size (if}
ll ^{enabled) If DRBE 31 28 DRB7 plus the memory space gap is greater than 512 MBytes then 512 MBytes of}
DRAM are available
The following 2 examples describe how the DRB Registers are programmed for cases of single-sided and
double-sided SIMMs on a motherboard having a total of 8 SIMM sockets
Example 1
The memory array is populated with eight single-sided 256-KByte x 36 SIMMs Two SIMMs are required for
each populated row making each populated row 2 MBytes in size Filling the array yields 8 MBytes total DRAM
The DRB Registers are programmed as follows
DRBE 3 0 ^e 0h
DRBE 7 4 ^e 0h
DRBE 11 8 ^e 0h
DRBE 15 12 ^e 0h
DRBE 19 16 ^e 0h
DRBE 23 20 ^e 0h
DRBE 27 24 ^e 0h
DRBE 31 28 ^e 0h
DRB0 ^e 02h
DRB1 ^e 02h
DRB2 ^e 04h
DRB3 ^e 04h
DRB4 ^e 06h
DRB5 ^e 06h
DRB6 ^e 08h
DRB7 ^e 08h
populated
empty row not double-sided SIMMs
populated
empty row not double-sided SIMMs
populated
empty row not double-sided SIMMs
populated
empty row not double-sided SIMMs max memory ^e 8 MBytes
Example 2
As an another example if the first four SIMM sockets are populated with 2 MByte x 36 double-sided SIMMs
and the last four SIMM sockets are populated with 16 MByte x 36 single-sided SIMMs then filling the array
yields 288 MBytes total DRAM The DRB Registers are programmed as follows
DRBE 3 0 ^e 0h
DRBE 7 4 ^e 0h
DRBE 11 8 ^e 0h
DRBE 15 12 ^e 0h
DRBE 19 16 ^e 0h
DRBE 23 20 ^e 0h
DRBE 27 24 ^e 1h
DRBE 31 28 ^e 1h
DRB0 ^e 08h
DRB1 ^e 10h
DRB2 ^e 18h
DRB3 ^e 20h
DRB4 ^e A0h
DRB5 ^e A0h
DRB6 ^e 20h
DRB7 ^e 20h
populated with 8 MBytes of double-sided SIMMs
the other 8 MBytes of the double-sided SIMMs
populated with 8 MBytes of double-sided SIMMs
the other 8 MBytes of the double-sided SIMMs
populated with 128 MBytes
empty row not double-sided SIMMs
populated with 128 MBytes
empty row not double-sided SIMMs max memory ^e 288 MBytes
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