82434LX Datasheet, PDF (102/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
290479 – 43
Figure 41 82434NX Connections to 512 KByte Cache with Standard SRAM
5 2 1 CYCLE LATENCY SUMMARY (82434NX)
Table 10 and Table 11 summarize the clock laten-
cies for CPU memory cycles which hit in the second-
ary cache
Table 10 Secondary Cache Latencies with
Synchronous Burst SRAM
Cycle Type
50 60 and
66 MHz
Burst Read
3-1-1-1
Burst Write
3-1-1-1
Single Read
3
Single Write
3
Pipelined Back-to-Back
Burst Reads
3-1-1-1-1-1-1-1
Burst Read Followed
by Pipelined Write
3-1-1-1-2
Table 11 Secondary Cache Latencies with
Standard Asynchronous SRAM (82434NX)
Cycle Type
50 60 and
66 MHz
Burst Read
3-2-2-2
Burst Write
4-2-2-2
Single Read
3
Single Write
4
Pipelined Back-to-Back
Burst Reads
3-2-2-2-3-2-2-2
Burst Read Followed
by Pipelined Write
3-2-2-2-4
102