82434LX Datasheet, PDF (93/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
290479 – 36
Figure 34 Snoop Hit to Unmodified Line in First Level Cache or Snoop Miss
The PCMC begins to service the snoop request by
asserting AHOLD causing the Pentium processor to
tri-state the address bus in the clock after assertion
In the case of a PCI master read cycle the PCMC
drives the DPRA (Drive PCI Read Address) com-
mand onto the HIG 4 0 lines causing the LBXs to
drive the PCI address onto the host address bus
For a write cycle the PCMC drives the DPWA (Drive
PCI Write Address to CPU Address Bus) command
on the HIG 4 0 lines also causing the LBXs to be-
gin driving the host address bus The PCMC then
asserts EADS initiating the snoop cycle to the
CPU The INV signal is asserted by the PCMC only
during snoops due to PCI master writes INV re-
mains negated during snoops due to PCI master
reads If the snoop results in a hit to a modified line
in the first level cache the Pentium processor as-
serts HITM The PCMC samples the HITM signal
two clocks after the CPU samples EADS asserted
to determine if the snoop hit in the first level cache
By this time the PCMC has completed an internal tag
lookup to determine if the line is in the second level
cache Since this snoop does not result in a write-
back the NOPC command is driven on the HIG 4 0
lines causing the LBXs to tri-state the address bus
The sequence ends with AHOLD negation
If the Pentium processor asserts ADS in the same
clock as the PCMC asserts AHOLD the PCMC will
assert BOFF in two cases First if the snoop cycle
hits a modified line in the first level cache the PCMC
will assert BOFF for 1 HCLK to re-order the write-
back around the currently sending cycle Second if
the snoop requires a write-back from the second lev-
el cache the PCMC will assert BOFF to enable
the write-back from the secondary cache SRAMs
Figure 35 depicts a snoop hit to a modified line in the
first level cache due to a PCI master memory read
cycle
The snoop cycle begins when the PCMC asserts
AHOLD causing the CPU to tri-state the address
bus The PCMC drives the DPRA (Drive PCI Read
Address) command on to the HIG 4 0 lines causing
the LBXs to drive the PCI address onto the host ad-
dress bus The PCMC then asserts EADS initiat-
ing the snoop to the first level cache INV is not
asserted since this is a PCI master read cycle INV is
only asserted with EADS when the snoop cycle is
in response to a PCI master write cycle As the CPU
is sampling EADS asserted the PCMC latches the
address Two clocks later the PCMC completes the
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