82434LX Datasheet, PDF (147/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
8 4 System Reset
Figure 75 shows the 82434LX and 82434NX PCMC
system reset connections The 82434LX and
82434NX PCMC reset logic monitors PWROK and
generates CPURST PCIRST and INIT
When asserted PWROK is an indicator to the PCMC
that VDD and HCLK have stabilized long enough for
proper system operation CPURST is asserted to ini-
tiate hard reset INIT is asserted to initiate soft reset
PCIRST is asserted to reset devices on PCI
Hard reset is initiated by the PCMC in response to
one of two conditions First hard reset is initiated
when power is first applied to the system PWROK
must be driven inactive and must not be asserted
until 1 ms after VDD and HCLK have stabilized at
their AC and DC specifications While PWROK is
negated the 82434LX asserts CPURST and
PCIRST PWROK can be asserted asynchronous-
ly When PWROK is asserted the 82434LX first en-
sures that it has been completely initialized before
negating CPURST and PCIRST CPURST is nega-
ted synchronously to the rising edge of HCLK
PCIRST is negated asynchronously
Figure 75 PCMC System Reset Logic
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