82434LX Datasheet, PDF (10/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
1 0 ARCHITECTURAL OVERVIEW
This section provides an 82430LX 82430NX PCIset
system overview that includes a description of the
bus hierarchy and bridges between the buses The
82430LX PCIset consists of the 82434LX PCMC and
82433LX LBX components plus either a PCI ISA
bridge or a PCI EISA bridge The 82430NX PCIset
consists of the 82434NX PCMC and 82433NX LBX
components plus either a PCI ISA bridge or a PCI
EISA bridge The PCMC and LBX provide the core
cache and main memory architecture and serve as
the Host PCI bridge An overview of the PCMC fol-
lows the system overview section
1 1 System Overview
The 82430LX 82430NX PCIset provides the Host
PCI bridge cache and main memory controller and
an I O subsystem core (either PCI EISA or PCI ISA
bridge) for the next generation of high-performance
personal computers based on the Pentium proces-
sor System designers can take advantage of the
power of the PCI (Peripheral Component Intercon-
nect) local bus while maintaining access to the large
base of EISA and ISA expansion cards Extensive
buffering and buffer management within the bridges
ensures maximum efficiency in all three buses (Host
CPU PCI and EISA ISA Buses)
For an ISA-based system the PCIset includes the
System I O (82378IB SIO) component (Figure 1) as
the PCI ISA bridge For an EISA-based system (Fig-
ure 2) the PCIset includes the PCI-EISA bridge
(82375EB PCEB) and the EISA System Component
(82374EB ESC) The PCEB and ESC work in tan-
dem to form the complete PCI EISA bridge
1 1 1 BUS HIERARCHY CONCURRENT
OPERATIONS
Systems based on the 82430LX 82430NX PCIset
contain three levels of buses structured in the fol-
lowing hierarchy
 Host Bus as the execution bus
 PCI Bus as a primary I O bus
 ISA or EISA Bus as a secondary I O bus
This bus hierarchy allows concurrency for simulta-
neous operations on all three buses Data buffering
permits concurrency for operations that crossover
into another bus For example the Pentium proces-
sor could post data destined to the PCI in the LBX
This permits the Host transaction to complete in
minimum time freeing up the Host Bus for further
transactions The Pentium processor does not have
to wait for the transfer to complete to its final desti-
nation Meanwhile any ongoing PCI Bus transac-
tions are permitted to complete The posted data is
then transferred to the PCI Bus when the PCI Bus is
available The LBX implements extensive buffering
for Host-to-PCI Host-to-main memory and PCI-to-
main memory transactions In addition the PCEB
ESC chip set and the SIO implement extensive buff-
ering for transfers between the PCI Bus and the
EISA and ISA Buses respectively
Host Bus
Designed to meet the needs of high-performance
computing the Host Bus features
 64-bit data path
 32-bit address bus with address pipelining
 Synchronous frequencies of 60 MHz and 66 MHz
 Synchronous frequency of 50 MHz (82430NX)
 Burst read and write transfers
 Support for first level and second level caches
 Capable of full concurrency with the PCI and
memory subsystems
 Byte data parity
 Full support for Pentium processor machine
check and DOS compatible parity reporting
 Support for Pentium processor System Manage-
ment Mode (SMM)
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