82434LX Datasheet, PDF (22/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
2 2 DRAM Interface
Signal Type
Description
RAS 5 0
out ROW ADDRESS STROBES The RAS 5 0 signals are used to latch the row
address on the MA 10 0 lines into the DRAMs Each RAS 5 0 signal corresponds
to one DRAM row The 82434LX PCMC supports up to 6 rows in the DRAM array
Each row is eight bytes wide These signals drive the RAS lines of the DRAM array
directly without external buffers
RAS 7 6
out ROW ADDRESS STROBES The 82434NX supports up to eight rows of DRAM
RAS 7 6 are used with RAS 5 0 to latch the row address on the MA 11 0 lines
into the DRAMs Each row is eight bytes wide These signals drive the RAS lines of
the DRAM array directly without external buffers
CAS 7 0
out COLUMN ADDRESS STROBES The CAS 7 0 signals are used to latch the
column address on the MA 10 0 lines into the DRAMs Each CAS 7 0 signal
corresponds to one byte of the eight byte-wide array These signals drive the CAS
lines of the DRAM array directly without external buffers In a minimum configuration
each CAS 7 0 line only has one SIMM load while the maximum configuration has 6
SIMM loads
WE
out DRAM WRITE ENABLE WE is asserted during both CPU and PCI master writes to
main memory During burst writes to main memory WE is asserted before the first
assertion of CAS 7 0 and is negated with the last CAS 7 0 The WE signal is
externally buffered to drive the WE inputs on the DRAMs
MA 10 0
out DRAM MULTIPLEXED ADDRESS MA 10 0 provide the row and column address to
the DRAM array The 82434LX uses MA 10 0 for the complete DRAM address bus
The MA 10 0 lines are externally buffered to drive the multiplexed address lines of
the DRAM array
MA11
out DRAM MULTIPLEXED ADDRESS MA11 provides the extra addressability for the
16M x 36 SiMMs that are supported by the 82434NX MA 11 0 provide the row and
column address to the DRAM array Like MA 10 0 MA11 is externally buffered to
drive the multiplexed address lines of the DRAM array
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