82434LX Datasheet, PDF (58/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 21 DRBE DRAM ROW BOUNDARY EXTENSION REGISTER
Address Offset
Default Value
Attribute
Size
68-6Bh
0000h
Read Write
32 bits
The DRBE Register is not implemented in the 82434LX This register contains an extension for each of the
DRAM Row Boundary (DRB) Registers Each nibble of the DRBE Register is concatenated with a DRB
Register (see DRB Register section for details on the use of the DRB and DRBE Registers)
290479 – 10
Bits
Description
31 0 EXTENSIONS FOR DRB0 THROUGH DRB7 Each nibble corresponds to a DRB The nibble of the
DRBE and its corresponding DRB are concatenated and used to indicate the boundaries between
rows of DRAM
3 2 22 ERRCMD ERROR COMMAND REGISTER
Address Offset
Default Value
Attribute
Size
70h
00h
Read Write
8 bits
The Error Command Register controls the PCMC responses to various system errors Bit 6 of the PCICMD
Register is the master enable for bit 3 of this register Bit 6 of the PCICMD Register must be set to 1 to enable
the error reporting function defined by bit 3 of this register Bits 6 and 8 of the PCICMD Register are the master
enables for bits 7 6 5 4 and 1 of this register Both bits 6 and 8 of the PCICMD Register must be set to 1 to
enable the error reporting functions defined by bits 7 6 5 4 and 1 of this register
58