82434LX Datasheet, PDF (94/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
290479 – 37
Figure 35 Snoop Hit to Modified Line in First Level Cache Post Memory and PCI
internal tag lookup to determine if the line is in the
second level cache In this instance the snoop hits
a modified line in the first level cache and misses in
the second level cache Thus the second level
cache is not involved in the write-back cycle The
PCMC allows the LBXs to stop driving the address
lines by driving NOPC command on the HIG 4 0
lines The CPU then drives the write-back cycle onto
the bus by asserting ADS and driving the write-
back data on the data lines even though AHOLD is
still asserted The write-back into the LBX buffers
occurs at a rate of 3-1-1-1 The PCMC drives
PCMWFQ on the HIG 4 0 lines for one clock caus-
ing the write data to be posted to both PCI and main
memory For the next three clocks the HIG 4 0
lines are driven to PCMWNQ posting the final three
Qwords to both PCI and main memory
A similar transfer from first level cache to the LBXs
occurs when a snoop due to a PCI master write hits
a modified line in the first level cache In this case
the write-back is transferred to the CPU-to-Memory
Posted Write Buffer If the line is in the second level
cache it is invalidated The cycle is similar to the
snoop cycle shown above with two exceptions The
PCMC drives the DPWA command on the HIG 4 0
lines instead of the DPRA command During the four
clocks where the PCMC drives BRDY active to the
CPU it also drives PCMWQ on the HIG 4 0 lines
causing the write to be posted to main memory
In both of the above cases where a write-back from
the first level cache is required AHOLD is asserted
until the write-back is complete If the CPU has be-
gun a read cycle directed to PCI and the snoop re-
sults in a hit to a modified line in the first level cache
BOFF is asserted for one clock to abort the CPU
read cycle and re-order the write-back cycle before
the read cycle
When a PCI master read or write cycle hits a modi-
fied line in the second level cache and either misses
in the first level cache or hits an unmodified line in
the first level cache a write-back from the second
level cache to the LBXs occurs When a PCI master
write snoop hits an unmodified line in the second
level cache and either misses in the first level cache
or hits an unmodified line in the first level cache no
data transfer from the second level cache occurs
The line is simply invalidated In the case of a PCI
master write cycle the line is invalidated in both the
first level and second level caches In the case of a
PCI master memory read cycle neither cache is in-
validated A PCI master read from main memory
which hits either a modified or unmodified line in the
second level cache is shown in Figure 36
94