82434LX Datasheet, PDF (141/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 4 PCI-to-Main Memory Cycles
7 4 1 PCI MASTER WRITE TO MAIN MEMORY
Figure 70 depicts a PCI master burst write to main
memory The PCI master begins by driving the ad-
dress on the AD 31 0 lines and asserting FRAME
Upon sampling FRAME active the PCMC drives
the LCPA command on the PIG 3 0 lines causing
the LBXs to retain the address that was latched on
the previous PCLK rising edge The PCMC then
samples MEMCS active indicating that the cycle
is directed to main memory The PCMC drives the
PPMWA command on the PIG 3 0 lines to move
the latched PCI address into the write buffer address
register The PCMC then drives the DPWA com-
mand on the HIG 4 0 lines enabling the LBXs to
drive the PCI master write address onto the host
address bus The PCMC asserts EADS to initiate a
first level cache snoop cycle and simultaneously be-
gins an internal second level cache snoop cycle
Since the snoop is a result of a PCI master write
INV is asserted with EADS HITM remains nega-
ted and the snoop either hits an unmodified line or
misses in the second level cache thus no write-back
cycles are required If the snoop hit an unmodified
line in either the first or second level cache the line
is invalidated The cycle is immediately forwarded to
the DRAM interface The four posted Dwords are
written to main memory as two Qwords with two
CAS 7 0 cycles In this example the DRAM inter-
face is configured for X-3-3-3 write timing thus each
CAS 7 0 low pulse is two HCLKs in length
The PCMC disconnects the cycle by asserting
STOP when one of the two four-Dword-deep PCI-
to-Memory Posted Write Buffers is full If the master
terminates the cycle before sampling STOP as-
serted then IRDY STOP and DEVSEL are
negated when FRAME is sampled negated If the
master intended to continue bursting then the mas-
ter negates FRAME when it samples STOP as-
serted IRDY STOP and DEVSEL are then
negated one clock later
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