82434LX Datasheet, PDF (89/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
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Figure 33 CPU Cache Read Miss Write-Back Line Fill with Burst SRAM (82434LX)
The CPU issues a memory read cycle which misses
in the second level cache In this instance a modi-
fied line in the second level cache must be written
back to main memory before the new line can be
filled into the cache The PCMC inspects the valid
and modified bits for each of the lines within the
addressed sector and writes back only the valid
lines within the sector that are marked modified
CA 6 5 are used to count through the lines within
the addressed sector When two or more lines must
be written back to main memory CA 6 5 count in
the direction from line 0 to line 3 after each line is
written back Figure 29 depicts the case of just one
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