82434LX Datasheet, PDF (149/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
8 5 82434NX Reset Sequencing
When PWROK is negated the 82434NX PCMC
drives the following signals low BRDY NA
AHOLD EADS
INV BOFF
KEN
PEN CPURST INIT CALE CADS 1 0
CADV 1 0 CAA 6 3 CAB 6 3 COE 1 0
CWE 7 0 HCLK A F are driven as soon as the
3 3V supply is active Note that CWE 7 0 low pre-
vents the second level cache data RAMs from driv-
ing the data bus even though COE 1 0 are also
driven low Also note that BOFF driven low caus-
es the CPU to tri-state all outputs to the 82434NX
PCMC and 82433NX LBX except HITM
SMIACT and PCHK This minimizes the number
of signals that the CPU may drive to the PCMC when
the 3 3V supply is active and the 5V supply is not
active
Figure 76 shows how the 82434NX sequences
CPURST and PCIRST in response to PWROK as-
sertion
Some PCI devices may drive 3 3V friendly signals
directly to 3 3V devices that are not 5V tolerant If
such signals are powered from the 5V supply they
must be driven low when PCIRST is asserted
Some of these signals may need to be driven high
before CPURST is negated PCIRST is negated
1 ms before CPURST to allow time for this to occur
Figure 76 82434NX Reset Sequencing at Power-Up
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