82434LX Datasheet, PDF (51/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 18 DRAMT DRAM TIMING REGISTER
Address Offset
Default Value
Attribute
Size
58h
00h
Read Write
8 bits
For the 82434LX this register controls the leadoff latency for CPU DRAM accesses
For the 82434NX this register provides additional control over DRAM timings One additional wait-state can
be independently added before the assertion of RAS the assertion of the first CAS or both This is to
allow more flexibility in the layout of the motherboard and in the selection of DRAM speed grades
Bits
Description
7 2 RESERVED
1 82434LX RESERVED
82434NX RAS WAIT-STATE (RWS) When RWS^e1 one additional wait state will be inserted
before RAS is asserted for row misses or page misses in 1-Active RAS mode and all cycles in
0-Active RAS mode This provides additional MA 11 0 setup time to RAS assertion
0 CAS WAIT-STATE (CWS) When CWS^e1 one additional wait state will be inserted before the first
assertion of CAS within a burst cycle There is no additional delay between CAS assertions This
provides additional MA 11 0 setup time to CAS assertion The CWS bit is typically reset to 0 for
60 MHz operation and set to 1 for 66 MHz operation
3 2 19 PAM PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM 6 0 )
Address Offset
Default Value
Attribute
59 – 5Fh
PAM0^e0Fh PAM 1 6 ^e00h
Read Write
The PCMC allows programmable memory and cacheability attributes on 14 memory segments of various sizes
in the 512 KByte–1 MByte address range Seven Programmable Attribute Map (PAM) Registers are used to
support these features Three bits are used to specify cacheability and memory attributes for each memory
segment These attributes are
RE Read Enable When RE^e1 the CPU read accesses to the corresponding memory segment are direct-
ed to main memory Conversely when RE^e0 the CPU read accesses are directed to PCI
WE Write Enable When WE^e1 the CPU write accesses to the corresponding memory segment are
directed to main memory Conversely when WE^e0 the CPU write accesses are directed to PCI
CE Cache Enable When CE^e1 the corresponding memory segment is cacheable CE must not be set to
1 when RE is reset to 0 for any particular memory segment When CE^e1 and WE^e0 the correspond-
ing memory segment is cached in the first and second level caches only on CPU coded read cycles
The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or disabled
For example if a memory segment has RE^e1 and WE^e0 the segment is Read Only The characteristics for
memory segments with these read write attributes are described in Table 2
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