82434LX Datasheet, PDF (132/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 0 PCI INTERFACE
The description in this section applies to both the
82434LX and 82434NX
7 1 PCI Interface Overview
The PCMC and LBXs form a high performance
bridge from the Pentium processor to PCI and from
PCI to main memory During PCI-to-main memory
cycles the PCMC and LBXs act as a target on the
PCI Bus allowing PCI masters to read from and
write to main memory During CPU cycles the
PCMC acts as a PCI master The CPU can then read
and write I O memory and configuration spaces on
PCI When the CPU accesses I O mapped and con-
figuration space mapped PCMC registers the PCMC
intercepts the cycles and does not forward them to
PCI Although these CPU cycles do not result in a
PCI bus cycle they are described in this section
since most of the PCMC internal registers are
mapped into PCI configuration space
7 2 CPU-to-PCI Cycles
7 2 1 CPU WRITE TO PCI
Figure 64 depicts a series of CPU memory writes
which are posted to PCI The CPU initiates the
cycles by asserting ADS and driving the memory
address onto the host address lines The PCMC
asserts NA in the clock after ADS allowing the
Pentium processor to drive another cycle onto the
host bus two clocks later The PCMC decodes the
memory address and drives PCPWL on the HIG 4 0
lines posting the host address bus and the low
Dword of the data bus to the LBXs The PCMC as-
serts BRDY terminating the CPU cycle with one
wait state Since NA is asserted in the second
clock of the first cycle the Pentium processor does
not insert an idle cycle after this cycle completes
but immediately drives the next cycle onto the bus
Thus the Pentium processor maximum Dword write
bandwidth of 89 MBytes second is achieved during
back-to-back Dword writes cycles Each of the fol-
lowing write cycles is posted to the LBXs in three
clocks
In this example the PCMC is parked on PCI and
therefore does not need to arbitrate for the bus
When parked the PCMC drives the SCPA command
on the PIG 3 0 lines and asserts DRVPCI causing
the host address lines to be driven on the PCI
AD 31 0 lines After the write is posted the PCMC
drives the DCPWA command on the PIG 3 0 lines
to drive the previously posted address onto the
AD 31 0 lines The PCMC then drives DCPWD onto
the PIG 3 0 lines to drive the previously posted
write data onto the AD 31 0 lines As this is occur-
ring on PCI the second write cycle is being posted
on the host bus In this case the second write is to a
sequential and incrementing address Thus the
PCMC leaves FRAME asserted converting the
write cycle into a PCI burst cycle The PCMC contin-
ues to drive the DCPWD command on the PIG 3 0
lines The LBXs advance the posted write buffer
pointer to point to the next posted Dword when
DCPWD is sampled on PIG 3 0 and TRDY is
sampled asserted Therefore if the target inserts a
wait-state by negating TRDY the LBXs continue
to drive the data for the current transfer The remain-
ing writes are posted on the host bus while the
PCMC and LBXs complete the writes on PCI
CPU I O write cycles to PCI differ from the memory
write cycle described here in that I O writes are nev-
er posted BRDY is asserted to terminate the cycle
only after TRDY is sampled asserted completing
the cycle on PCI
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