82434LX Datasheet, PDF (111/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 4 3 Read Row Miss
Figure 46 depicts a CPU burst read row miss from
DRAM The 82434LX decodes the CPU address as
a row miss and switches from initially driving the col-
umn address to driving the row address on the
MA 10 0 lines The RAS signal that was asserted
is negated and the RAS for the currently accessed
row is asserted The PCMC then switches the
MA 10 0 lines to drive the column address and as-
serts CAS 7 0 CMR (CPU Memory Read) is driv-
en on the HIG 4 0 lines to enable the memory data
to host data path through the LBXs The PCMC ad-
vances the MA 1 0 lines through the Pentium proc-
essor burst order negating and asserting
CAS 7 0 to read each Qword The host data is
latched on the falling edge of MDLE when
CAS 7 0 are negated The latch is opened again
when MDLE is sampled asserted by the LBXs The
LBXs tri-state the host data bus when HIG 4 0
change to NOPC and MDLE rises A single read row
miss from DRAM is similar to the first read of this
sequence The HIG 4 0 lines are driven to NOPC
when BRDY is asserted
Figure 46 Burst DRAM Read Cycle-Row Miss
290479 – 55
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