82434LX Datasheet, PDF (38/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Type 0 Access
If the Forward Register contains 00h a Type 0 configuration access is generated on the PCI Bus (Figure 6) For
type 0 configuration cycles AD 1 0 ^e00 Host CPU address bits A 7 2 are not translated and become
AD 7 2 on the PCI Bus AD 7 2 select one of the 256 8-bit I O locations in the PCI configuration space The
FUNCTION NUMBER field from the CSE Register (CSE 3 1 ) is driven on AD 10 8 Host CPU address bits
A 11 8 are mapped to an IDSEL input for each of the 16 possible PCI devices The IDSEL input for each PCI
device must be hard-wired to one of the AD 31 16 signals on the PCI Bus AD16 is reserved for the PCMC
When CPU address A 11 8 ^eFh PCI address bits A31^e1 and A 30 16 ^e00h Other devices on the PCI Bus
should not use AD16 Note that when A 11 8 ^e0h an access to the PCMC internal registers occurs and the
cycle is not forwarded to the PCI Bus
Figure 6 Mechanism 2 Type 0 Host-to-PCI Address Mapping
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