82434LX Datasheet, PDF (100/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
290479 – 41
Figure 39 512 KByte Secondary Cache Standard Dual-Byte-Select (Asynch) SRAM 50 60 66 MHz
Figure 38 depicts the PCMC connections to a
512 KByte burst SRAM secondary cache when the
PCMC is configured for 50 60 or 66 MHz operation
Host address lines HA 18 3 are connected directly
to the SRAM address lines A 15 0 ADS from the
CPU is connected to ADSP on the SRAMs
CADV0 implements the address advance (ADV )
functionality A new signal CCS is multiplexed
onto the CADV1 pin When bit 2 in the SCC regis-
ter is set to 1 SRAMs containing logic which gates
ADSP with CS must be used When negated
CCS prevents the SRAMs from latching a new ad-
dress due to a pipelined ADS from the CPU during
cache line fills Note that unlike the burst SRAM
configuration with the 82430 PCIset no external
latch is used between the CPU address bus and the
SRAM address lines The SRAM Connectivity bit (bit
2) in the Secondary Cache Control register (offset
52h) must be set to 1 when using this cache configu-
ration
If the tag lookup results in a miss in the cache and
the sector to be replaced contains one or more mod-
ified lines the PCMC drives the write-back address
from the A 18 3 lines on the host bus Although not
used in the write-back A 31 19 (or A 31 18 in the
case of a 256 KB cache) are driven to valid logic
levels by the PCMC
Figure 39 depicts the 82434NX PCMC connections
to a 512 KByte standard asynchronous SRAM sec-
ondary cache Figure 40 depicts the 82434NX con-
nections to a 256 KByte asynchronous SRAM sec-
ondary cache Host address lines HA 18 7 are
driven through an external latch to form the upper
SRAM address lines CA 18 7 CA 6 3 are
driven from the PCMC Figure 41 depicts the
82434NX PCMC connections to a 512 KByte stan-
dard SRAM secondary cache with dual-write-enable
SRAMs
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