82434LX Datasheet, PDF (14/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
1 2 1 CACHE OPERATIONS
The PCMC provides the control for a second level
cache memory array implemented with either stan-
dard asynchronous SRAMs or synchronous burst
SRAMs The data memory array is external to the
PCMC and located on the Host address data bus
Since the Pentium processor contains an internal
cache there can be two separate caches in a Host
subsystem The cache inside the Pentium processor
is referred to as the first level cache (also called
primary cache) A detailed description of the first lev-
el cache is beyond the scope of this document The
PCMC cache control circuitry and associated exter-
nal memory array is referred to as the second level
cache (also called secondary cache) The second
level cache is unified meaning that both CPU data
and instructions are stored in the cache The
82434LX PCMC supports both write-through and
write-back caching policies and the 82434NX sup-
ports write-back
The optional second level cache memory array can
be either 256-KBytes or 512-KBytes in size The
cache is direct-mapped and is organized as either
8K or 16K cache lines of 32 bytes per line
In addition to the cache data RAM the second level
cache contains a 4K set of cache tags that are inter-
nal to the PCMC Each tag contains an address that
is associated with the corresponding data sector
(2 lines for a 256 KByte cache and 4 lines for a
512 KByte cache) and two status bits for each line in
the sector
During a main memory read or write operation the
PCMC first searches the cache If the addressed
code or data is in the cache the cycle is serviced by
the cache If the addressed code or data is not in the
cache the cycle is forwarded to main memory
For the write-through (82434LX only) and write-back
(both 82434LX and 82434NX) policies the cache
operation is determined by the CPU read or write
cycle as follows
Write Cycle
If the caching policy is write-through and the write
cycle hits in the cache both the cache and main
memory are updated Upon a cache miss only
main memory is updated The cache is not updat-
ed (no write-allocate)
If the caching policy is write-back and the write
cycle hits in the cache only the cache is updated
main memory is not affected Upon a cache miss
only main memory is updated The cache is not
updated (no write-allocate)
Read Cycle
Upon a cache hit the cache operation is the same
for both write-through and write-back In this case
data is transferred from the cache to the CPU
Main memory is not accessed
Figure 3 Second Level Cache Organization
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