82434LX Datasheet, PDF (49/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 16 PBC PCI READ WRITE BUFFER CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
54h
00h
Read Write
8 bits
The PBC Register enables and disables PCI-to-main memory write posting and permits single CPU-to-PCI
writes to be assembled into PCI burst cycles
Bits
Description
7 3 RESERVED
2 LBXs CONNECTED TO TRDY The TRDY pin on the LBXs can be connected either to the PCI
TRDY signal or to ground The cycle time for CPU-to-PCI writes is improved if TRDY is connected
to the LBXs Since there are two LBXs used in a system connecting this signal to the LBXs increases
the electrical loading of TRDY by two loads When the LBXs are externally hard-wired to TRDY
this bit should be set to 1 Note that this should be done prior to the first Host-to-PCI write or data
corruption will occur Setting this bit to 1 enables the capability of CPU-to-PCI writes at 2-1-1-1
(PCI clocks) When this bit is 0 the LBXs are not connected to TRDY and CPU-to-PCI writes are
completed at 2-2-2-2 timing
1 PCI BURST WRITE ENABLE (PBWE) This bit enables and disables PCI Burst memory write cycles
for back-to-back sequential CPU memory write cycles to PCI When PBWE is set to 1 PCI burst
writes are enabled When PBWE is reset to 0 PCI burst writes are disabled and each single CPU write
to PCI invokes a single PCI write cycle (each cycle has an associated FRAME sequence)
0 PCI-TO-MEMORY POSTING ENABLE (PMPE) This bit enables and disables posting of PCI-to-
memory write cycles The posting occurs in a pair of four Dword-deep buffers in the LBXs When
PMPE is set to 1 these buffers are used to post PCI-to-main memory write data When PMPE is reset
to 0 PCI write transactions to main memory are limited to single transfers The PCMC asserts
STOP with the first TRDY to disconnect the PCI Master
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