82434LX Datasheet, PDF (144/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
8 0 SYSTEM CLOCKING AND RESET
8 1 Clock Domains
The 82434LX and 82434NX PCMCs and 82433LX
and 82433NX LBXs operate based on two clocks
HCLK and PCLK The CPU second level cache and
the DRAM interfaces operate based on HCLK The
PCI interface timing is based on PCLK
8 2 Clock Generation and Distribution
Figure 72 shows an example of the 82434LX and
82434NX PCMC host clock distribution in the CPU
cache and memory subsystem HCLK is distributed
to the CPU PCMC LBXs and the second level
cache SRAMs (in the case of a burst SRAM second
level cache)
The host clock originates from an oscillator which is
connected to the HCLKOSC input on the PCMC
The PCMC generates six low skew copies of HCLK
HCLKA–HCLKF Figure 72 shows an example of a
host clock distribution scheme for a uni-processor
system In this figure clock loading is balanced with
each HCLK output driving two loads in the system
Each clock output should drive a trace of length k
with stubs at the end of the trace of length l connect-
ing to the two loads The l and k parameters should
be matched for each of the six clock outputs to mini-
mize overall system clock skew One of the HCLK
outputs is used to clock the PCMC and the Pentium
processor Because the clock driven to the PCMC
HCLKIN input and the Pentium processor CLK input
originates with the same HCLK output clock skew
between the PCMC and the CPU can be kept lower
than between the PCMC and other system compo-
nents Another copy of HCLK is used to clock the
LBXs A 256 KByte burst SRAM second level cache
can be implemented with eight 32 KByte x 9 syn-
chronous SRAMs The four remaining copies of
HCLK are used to clock the SRAMs Each HCLK
output drives two SRAMs A 512 KByte second level
cache is implemented with four 64 KByte x 18 syn-
chronous SRAMs Two of the four extra copies are
used to clock the SRAMs while the other two are
unused Any one of the HCLK outputs can be used
to clock the PCMC and Pentium processor the two
LBXs or any pair of SRAMs All six copies are identi-
cal in drive strength
Figure 73 depicts the PCI clock distribution
Figure 72 HCLK Distribution Example
290479 – 82
144