82434LX Datasheet, PDF (108/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 3 CYCLE TIMING SUMMARY
The 82434LX PCMC DRAM performance is summa-
rized in Table 13 for all CPU read and write cycles
Table 13 CPU to DRAM Performance Summary
Cycle Type
Burst
x-4-4-4
Timing
Single
x-4-4-4
Timing
Read Page Hit
7-4-4-4
7
Read Row Miss
11-4-4-4
11
Read Page Miss
14-4-4-4
14
Posted Write WT L2
3-1-1-1
3
Posted Write WB L2
4-1-1-1
4
Write Page Hit
12-4-4-4
12
Write Row Miss
13-4-4-4
13
Write Page Miss
16-4-4-4
16
0-Active RAS
Mode Read
10-4-4-4
10
0-Active RAS
Mode Write
12-4-4-4
12
CPU writes to the CPU-to-Memory Posted Write
Buffer are completed at 3-1-1-1 when the second
level cache is configured for write-through mode and
4-1-1-1 when the cache is configured for write-back
mode Table 14 shows the refresh performance in
CPU clocks
Table 14 Refresh Cycle Performance
Refresh
Type
Hidden RAS only CAS before
Refresh Refresh RAS
Single
12
13
14
Burst of Four 48
52
56
6 1 4 CPU TO DRAM BUS CYCLES
This section describes the CPU-to-DRAM cycles for
the 82434LX
6 1 4 1 Read Page Hit
Figure 44 depicts a CPU burst read page hit from
DRAM The 82434LX PCMC decodes the CPU ad-
dress as a page hit and drives the column address
onto the MA 10 0 lines CAS 7 0 are then assert-
ed to cause the DRAMs to latch the column address
and begin the read cycle CMR (CPU Memory Read)
is driven on the HIG 4 0 lines to enable the memory
data to host data path through the LBXs The PCMC
advances the MA 1 0 lines through the Pentium
processor burst order negating and asserting
CAS 7 0 to read each Qword The host data is
latched on the falling edge of MDLE when
CAS 7 0 are negated The latch is opened again
when MDLE is sampled asserted by the LBXs The
LBXs tri-state the host data bus when HIG 4 0
change to NOPC and MDLE rises A single read
page hit from DRAM is similar to the first read of this
sequence The HIG 4 0 lines are driven to NOPC
when BRDY is asserted
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